Higher circuit density and faster switching speed have been a major focus of recent developments in semiconductor technology. There are two related factors that limit the switching speed of semiconductor devices. First, in a bipolar transistor, for example, is the parasitic resistance between the base contact and the active area of the transistor. Secondly is the parasitic capacitance between the base region and the collector region. Each time the transistor switches, the base current charges or discharges the parasitic capacitance. The base current is further impeded by the parasitic base resistance. The speed of the semiconductor device is increased by reducing the product of the parasitic base resistance and the parasitic capacitance.
Metal Oxide Semiconductor (MOS) devices are also susceptible to parasitic capacitances and parasitic resistances. Asymmetric MOSFET devices are known MOSFET devices for reducing parasitic capacitances . In such MOSFETs the source and drain regions are not symmetrically doped because of different implant dosages or because of asymmetric source and drain extension implant relative to the gate channel conductor. For example, U.S. Pat. No. 6,746,924 discloses a method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. The source and drain extensions are asymmetric in the sense that the extension on the source side overlaps with the gate by a distance that is different from the overlap with the gate on the drain side. In this reference a photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor. Then damaged portions of the nitride layer are removed while leaving undamaged portions of the nitride layer as a nitride mask to protect at least a portion of each drain region and at least one gate sidewall from a subsequent dopant implant, which is performed into the source regions and the drain regions while using the undamaged portions of the nitride layer as a mask to form the asymmetric extension MOSFET device.
While the MOSFET device shown in the aforementioned reference may reduce the parasitic capacitance, there remains a need to provide a MOSFET device in which the parasitic resistances are reduced.